1. Field of the Invention
The present invention relates to a recording apparatus and a control method for a recording apparatus.
2. Description of the Related Art
At present, there are apparatuses that write image data, audio data, and so on into a recording medium such as a memory card or read out and play back data recorded into a recording medium. The reading and writing of data between an apparatus to which a recording medium is connected (a host apparatus) and the recording medium is carried out based on a clock signal generated by the host apparatus. The data to be written or read is sent/received, or a response to a command is received, after the host apparatus sends a single clock pulse of the clock signal. The clock pulse and the data, the response, or the like are thus not necessarily sent/received in perfect synchronization. For example, in the case where the host apparatus reads out data from a recording medium such as an SD memory card, there is delay, equivalent to a standardized fixed value, from when the host apparatus supplies the clock pulse to the recording medium to when the data is actually sent. Accordingly, the host apparatus obtains the data sent from the recording medium by latching the data sent from the recording medium at a timing delayed from the sending of the clock pulse by an amount equivalent to the fixed value.
Recent years have seen increases in data rates for reading and writing from and to such recording media, making it necessary to accelerate the sending of clock pulses, and it has thus become difficult to use fixed values to define amounts of delay from clock pulses for obtaining data. Meanwhile, UHS-I (Ultra High Speed-I), which is a high-speed standard for SD memory cards, defines reading out data after adjusting the timing of the data latch on a card-by-card basis, when reading out data using a high-speed clock. Adjusting the latch timing in this manner is called “tuning” (see Japanese Patent Laid-Open No. 2012-54715, for example).
In the tuning process, the host apparatus varies the clock phase (delay amount) and determines whether or not the correct data has been read out from the recording medium at each phase, and then selects the optimal phase as the latch timing based on the determination result for each phase.
However, there have been cases where the phases in which the correct data is read out are spread over a plurality of ranges, due to the capabilities or changes in temperature of the delay element that varies the clock phase, or individual differences between recording media and so on. In such cases, the host apparatus may select, as the latch timing, a phase that falls within a range that is not necessarily optimal.